`timescale 1ns / 1ps
//********************************************************************** 
// -------------------------------------------------------------------
// Disclaimers
// -------------------------------------------------------------------
// When you use this source file, please note that the author assumes 
// no legal or non-legal responsibility for any consequences of your use 
// of it including, but not limited to, the specific use of the code or 
// liability to you for infringement of any patent, copyright or other 
// intellectual property rights.
// If you do not agree to the terms, please do not use the file and 
// delete the file promptly.
// -------------------------------------------------------------------
// Copyright Notice
// -------------------------------------------------------------------
// This source file may be used for personal study, provided that this 
// copyright notice is not removed from the file.
// and that derivative works of this source file contain the original 
// copyright notice and related disclaimers.
// For commercial use, please contact the author for authorization, 
// otherwise the author reserves all rights.
// ------------------------------------------------------------------- 
// Author: Geeker_FPGA 
// Email:geeker_fpga@uisrc.com
// Date:2022/04
// Description: 
//  
// 
// Web:http://www.uisrc.com
//------------------------------------------------------------------- 
//*********************************************************************/

module shift_ip#(
	parameter DATA_W = 8,
	parameter DATA_D = 8
)
(
	D,
	CLK,
	CE, 
	Q
);
input                            CLK;
input                            CE;
input        [DATA_W-1:0]        D;
output       [DATA_W-1:0]        Q;

reg [DATA_W-1:0]  D_REG[0:DATA_D-1];

always@(posedge CLK )
begin
	if(CE)
		D_REG[0] <= D;    
	else
		D_REG[0] <= 'd0;        
end

genvar i;
generate
	for(i=1;i<DATA_D;i=i+1)
	begin:SHFTER_IP
		always@(posedge CLK )
		begin
			if(CE)
				D_REG[i] <= D_REG[i-1];
			else
				D_REG[i] <= 'd0;
		end
	end

endgenerate

assign Q 	= D_REG[DATA_D - 1];

endmodule